The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of forming a structure for a field-effect transistor and related structures.
Device structures for a field-effect transistor generally include a source, a drain, and a gate electrode configured to switch carrier flow in a channel formed in a semiconductor body between the source and drain. The body and channel of a planar field-effect transistor are arranged beneath the top surface of a substrate on which the gate electrode is supported. When a control voltage exceeding a designated threshold voltage is applied to the gate electrode, the flow of carriers in the channel produces a device output current.
A fin-type field-effect transistor (FinFET) is a non-planar device structure for a field-effect transistor that may be more densely packed in an integrated circuit than planar field-effect transistors. A FinFET includes a fin, heavily-doped source/drain regions, and a gate electrode that wraps around the fin. During operation, a channel for carrier flow is formed in the fin between the source/drain regions. In comparison with planar field-effect transistors, the arrangement between the gate structure and fin improves control over the channel and reduces the leakage current when the FinFET is in its ‘Off’ state. This, in turn, lowers threshold voltages in comparison with planar field-effect transistors, and results in improved performance and lowered power consumption.
Nanosheet field-effect transistors have been developed that may permit additional increases in packing density in an integrated circuit. The body of a nanosheet field-effect transistor includes multiple nanosheet channel layers vertically stacked in a three-dimensional array. Sections of a gate stack may surround all sides of the individual nanosheet channel layers in a gate-all-around arrangement. The nanosheet channel layers are initially arranged in a layer stack with sacrificial layers composed of a material (e.g., silicon-germanium) that can be etched selectively to the material (e.g., silicon) constituting the nanosheet channel layers. The sacrificial layers are etched and removed in order to release the nanosheet channel layers, and to provide spaces for the formation of the gate stack.